The field of this invention relates to an apparatus for reducing current usage in radio frequency (RF) communication units, and in particular for reducing current in sliced RF communication units.
In the field of radio frequency (RF) communication units, slicing of components and circuits across a number of parallel integrated circuits (ICs) is utilised in order to reduce the amount of current drawn by the RF communication units, thereby increasing their efficiency and, in the case of wireless devices, potentially enhancing battery life.
Referring to FIG. 1, a known slicing architecture 100 is illustrated. In this known architecture, a local oscillator input 102 provides an LO signal 120 to a first input 110 of AND logic gate 109. A divide-by-N module, for example a divide-by-2 module, 104 increases the duty cycle of LO signal 120 and outputs a DIV2 signal 122 to a second input 111 of the AND logic gate 109. In this case, the duty cycle of DIV2 122 is preconfigured so that the AND logic gate 109 outputs a 25% duty cycle square wave local oscillator buffered signal (LOBUF) 124.
The AND logic gate 109 that generates the LOBUF signal 124 is a noise sensitive module and requires a high current to maintain signal integrity in both signal strength and noise level of LOBUF 124. As a result, these circuits generally consume a large amount of current. In the known slicing architecture 100, the AND logic gate 109 is grouped on a single slice 128.
A disadvantage of the slicing architecture 100 is that the divide-by-N module 104 has to drive a plurality of slices 132 comprising noise sensitive circuits (AND logic gates 109) and, therefore, the divide-by-N module 104 consumes a large amount of current. This potentially reduces the overall efficiency of the slicing architecture 100. In effect, the divide-by-N module 104 is designed to meet a worst-case scenario and thereby has a significant current overhead.
It may be advantageous to further improve current saving of the slicing architecture 100.
U.S. Pat. No. 6,072,994 discloses a digitally programmable multifunctional radio having a common transmit module. This common transmit module is internally programmably reconfigurable and self-contained for channelized operation in each of a plurality of different radio modes, for digitally processing a bit stream into a digital signal, converting the digital signal into an analog signal and frequency translating the analog signal into an RF signal. An antenna interface module is coupled to the antenna and the common transmit module, for performing further processing of the RF signal and for providing the further processed RF signal to the antenna for transmission. The common transmit module and the antenna inter-face module are partitioned such that the common transmit module includes components that are programmably reconfigurable for operation in all of the plurality of different radio modes.
Thus, a need exists for an improved transmitter architecture, receiver, and/or transceiver that may be capable of further reducing current consumption when compared to the prior art.